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m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 1 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. 240pin unbuffered ddr2 sdram module based on 64mx8 ddr2 sdram features ? jedec standard 240-pin dual in-line memory module ? 64mx64 and 128mx64 ddr2 unbuffered dimm based on 64mx8 ddr2 sdram ? performance: pc2-5300 speed sort 3c dimm cas latency * 5 unit f ck clock frequency 333 mhz t ck clock cycle 3 ns f dq dq burst frequency 667 mhz ? intended for 333mhz applications ? inputs and outputs are sstl-18 compatible ? v dd = v ddq = 1.8volt 0.1 ? sdrams have 4 internal banks for concurrent operation ? differential clock inputs ? data is read or written on both clock edges ? bi-directional data strobe with one clock cycle preamble and one-half clock post-amble ? address and control signals are fully synchronous to positive clock edge ? write latency = read latency - 1 ? programmable operation: - device cas latency: 3, 4, 5 - burst type: sequential or interleave - burst length: 4, 8 - operation: burst read and write ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? 14/10/1 addressing (row/column/bank) ? m1y51264tu88a2b ? 14/10/2 addressing (row/column/bank) - m1y1g64tu8ha2b ? 7.8 s max. average periodic refresh interval ? serial presence detect ? on die termination (odt) ? gold contacts ? sdrams in 60-ball fbga package ? rohs compliant product description m1y51264tu88a2b and m1y1g64tu8ha2b are 240-pin double data rate 2 (ddr2) synchronous dram unbuffered dual in-line memory module (udimm), organized as a one-rank 64mx64 and tw o ranks 128mx64 high-speed memory array. modules use eight 64mx8 (m1y51264tu88a2b) and sixteen 64mx8 (m1y1g64tu8ha 2b) ddr2 sdrams in fbga packages. these dimms are manufactured using raw cards developed for br oad industry use as referenc e designs. the use of thes e common design files minimi zes electrical variation between suppliers. all elixir ddr2 sdram dimms provide a high-perfo rmance, flexible 8-byte interface in a 5.25? long space-saving footprint. the dimm is intended for use in applications operating up to 333m hz clock speeds and achieves hi gh-speed data transfer rates of up to 667mhz. prior to any access operation, the device cas latency and burst / length / operation type must be programmed into the dimm by address inputs a0-a13 and i/o inputs ba0 and ba1 using the mode register set cycle. the dimm uses serial presence- detect implemented via a serial 2,048-bit eeprom using a standard iic protocol. the first 128 byt es of serial pd data are programmed and locked during module assembly. the remaining 128 bytes are available for use by the customer.
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 2 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ordering information part number speed organization leads power note m1y51264tu88a2b-3c 64mx64 M1Y1G64TU8HA2B-3C 333mhz (3ns @ cl = 5) ddr2-667 pc2-5300 128mx64 gold 1.8v pin description ck0, ck0 differential clock inputs dq0-dq63 data input/output cke0, cke1 clock enable cb0-cb7 ecc check bit data input/output ras row address strobe dqs0-dqs8 bidirectional data strobes cas column address strobe dm0-dm8/dqs9-17 input data mask/high data strobes we write enable dqs0 - dqs17 differential data strobes cs0 , cs1 chip selects v dd power (1.8v) a0-a9, a11-a13 address inputs v ref ref. voltage for sstl_18 inputs a10/ap column address input/auto-precharge v ddspd serial eeprom positive power supply ba0, ba1 sdram bank address inputs v ss ground reset reset pin scl serial presence detect clock input odt0, odt1 active termination control lines sda serial presence detect data input/output nc no connect sa0-2 serial presence detect address inputs
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 3 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pinout pin front pin front pin front pin back pin back pin back 1 v ref 42 nc 82 v ss 121 v ss 162 nc 202 dm4 2 v ss 43 nc 83 dqs4 122 dq4 163 v ss 203 nc 3 dq0 44 v ss 84 dqs4 123 dq5 164 nc 204 v ss 4 dq1 45 nc 85 v ss 124 v ss 165 nc 205 dq38 5 v ss 46 nc 86 dq34 125 dm0, dqs9 166 v ss 206 dq39 6 dqs0 47 v ss 87 dq35 126 dqs9 167 nc 207 v ss 7 dqs0 48 nc 88 v ss 127 v ss 168 nc 208 dq44 8 v ss 49 nc 89 dq40 128 dq6 169 v ss 209 dq45 9 dq2 50 v ss 90 dq41 129 dq7 170 v ddq 210 v ss 10 dq3 51 v ddq 91 v ss 130 v ss 171 cke1 211 dm5 11 v ss 52 cke0 92 dqs5 131 dq12 172 v dd 212 nc 12 dq8 53 v dd 93 dqs5 132 dq13 173 nc 213 v ss 13 dq9 54 nc 94 v ss 133 v ss 174 nc 214 dq46 14 v ss 55 nc 95 dq42 134 dm1, dqs10 175 v ddq 215 dq47 15 dqs1 56 v ddq 96 dq43 135 dqs10 176 a12 216 v ss 16 dqs1 57 a11 97 v ss 136 v ss 177 a9 217 dq52 17 v ss 58 a7 98 dq48 137 ck1 178 v dd 218 dq53 18 nc 59 v dd 99 dq49 138 ck1 179 a8 219 v ss 19 nc 60 a5 100 v ss 139 v ss 180 a6 220 ck2 20 v ss 61 a4 101 sa2 140 dq14 181 v ddq 221 ck2 21 dq10 62 v ddq 102 nc 141 dq15 182 a3 222 v ss 22 dq11 63 a2 103 v ss 142 v ss 183 a1 223 dm6 23 v ss 64 v dd 104 dqs6 143 dq20 184 v dd 224 nc 24 dq16 key 105 dqs6 144 dq21 key 225 v ss 25 dq17 65 v ss 106 v ss 145 v ss 185 ck0 226 dq54 26 v ss 66 v ss 107 dq50 146 dm2 186 ck0 227 dq55 27 dqs2 67 v dd 108 dq51 147 nc 187 v dd 228 v ss 28 dqs2 68 nc 109 v ss 148 v ss 188 a0 229 dq60 29 v ss 69 v dd 110 dq56 149 dq22 189 v dd 230 dq61 30 dq18 70 a10/ap 111 dq57 150 dq23 190 ba1 231 v ss 31 dq19 71 ba0 112 v ss 151 v ss 191 v ddq 232 dm7 32 v ss 72 v ddq 113 dqs7 152 dq28 192 ras 233 nc 33 dq24 73 we 114 dqs7 153 dq29 193 cs0 234 v ss 34 dq25 74 cas 115 v ss 154 v ss 194 v ddq 235 dq62 35 v ss 75 v ddq 116 dq58 155 dm3 195 odt0 236 dq63 36 dqs3 76 cs1 117 dq59 156 nc 196 a13 237 v ss 37 dqs3 77 odt1 118 v ss 157 v ss 197 v dd 238 v ddspd 38 v ss 78 v ddq 119 sda 158 dq30 198 v ss 239 sa0 39 dq26 79 v ss 120 scl 159 dq31 199 dq36 240 sa1 40 dq27 80 dq32 160 v ss 200 dq37 41 v ss 81 dq33 161 nc 201 v ss
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 4 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0, ck1, ck2 (sstl) positive edge the positive line of the differential pair of sy stem clock inputs which drives the input to the on-dimm pll. all the ddr2 sdram address and control inputs are sampled on the rising edge of their associated clocks. ck0 , ck1 , ck2 (sstl) negative edge the negative line of the differential pair of syst em clock inputs which drives the input to the on-dimm pll. cke0, cke1 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, or the self refresh mode. cs0 , cs1 (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when the comma nd decoder is disabled, new commands are ignored but previous operations continue. ras , cas , we (sstl) active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. v ref supply reference voltage for sstl-18 inputs v ddq supply isolated power supply for the ddr sdram out put buffers to provide improved noise immunity odt0, odt1 input active high on-die termination control signals ba0, ba1 (sstl) - selects which sdram bank is to be active. a0 ? a9 a10/ap a11 ? a13 (sstl) - during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-a9, a11 defines the column address (ca0-ca10) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0/ba1 define the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high a ll 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre-charge. dq0 ? dq63 cb0 ? cb7 (sstl) active high data and check bit input/output pins. check bits are only applicable on the x72 dimm configurations. v dd, v ss supply power and ground for the ddr sdram input buffers and core logic dqs0 ? dqs8 dqs0 ? dqs8 (sstl) negative and positive edge data strobe for input and output data dm0 ? dm8 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no e ffect. dm8 is associated with check bits cb0-cb7, and is not used on x64 modules. sa0 ? sa2 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bi-directional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pull-up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pull-up. v ddspd supply serial eeprom positive power supply.
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 5 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. functional block diagram (512mb, 1 rank, 64mx8 ddr2 sdrams) serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 serial pd v ddspd v ddq v dd v ref v ss v ddid d0-d8 d0-d8 d0-d8 d0-d8 strap : see note 4 cs0 dm1 dqs1 dqs1 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 cs d1 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dqs2 dqs2 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 cs d2 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dm2 dqs3 dqs3 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 cs d3 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dm3 dm5 dqs5 dqs5 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 cs d5 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dm6 dqs6 dqs6 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 cs d6 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dm7 dqs7 dqs7 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 cs d7 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dqs4 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 cs d4 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dqs4 dm4 dm0 dqs0 dqs0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 cs d0 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm ba0-ba1 a0-a13 ras cas cke0 odt0 we a0-a13 : sdrams d0-d8 ba0-ba1 : sdrams d0-d8 ras : sdrams d0-d8 cke : sdrams d0-d8 cas : sdrams d0-d8 odt : sdrams d0-d8 we : sdrams d0-d8 notes : 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/cs relationships are maintained as shown. 3. dq/dqs/ dqs resistors are 22 ohms +/- 5% 4. bax, ax, ras , cas , we resistors are 5.1 ohms +/- 5% 5. address and control resistors are 22 ohms +/- 5%
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 6 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. functional block diagram (1gb, 2 rank, 64mx8 ddr2 sdrams) serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 serial pd v ddspd v ddq v dd v ref v ss v ddid d0-d8 d0-d8 d0-d8 d0-d8 strap : see note 4 cs0 notes : 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/cs relationships are maintained as shown. 3. dq/dqs/ dqs resistors are 22 ohms +/- 5% 4. bax, ax, ras , cas , we resistors are 5.1 ohms +/- 5% 5. address and control resistors are 22 ohms +/- 5% dm1 dqs1 dqs1 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dqs2 dqs2 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dm2 dqs3 dqs3 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 dm3 dm0 dqs0 dqs0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dm5 dqs5 dqs5 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 cs d5 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dm6 dqs6 dqs6 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 cs d6 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dm7 dqs7 dqs7 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 cs d7 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dqs4 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 cs d4 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm dqs4 dm4 cs d1 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d2 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d3 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d0 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d9 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d10 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d11 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d8 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d13 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d14 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d15 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm cs d12 dqs dqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 dm ba0-ba1 a0-a13 ras cas cke0 we a0-a13 : sdrams d0-d17 ba0-ba1 : sdrams d0-d17 ras : sdrams d0-d17 cke : sdrams d0-d8 cas : sdrams d0-d17 we : sdrams d0-d17 cke1 cke : sdrams d9-d17 odt0 odt : sdrams d0-d8 odt1 odt : sdrams d9-d17 cs1
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 7 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect ? part 1 of 2 (512mb) 64mx64 1 bank unbuffered ddr2 sdram dimm based on 64mx8, 4banks, 8k refresh, 1.8v ddr2 sdrams with spd spd entry value serial pd data entry (hexadecimal) note byte description ddr2 -667 (-3c) ddr2 -667 (-3c) 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type ddr2-sdram 08 3 number of row addresses on assembly 14 0e 4 number of column addresses on assembly 10 0a 5 number of dimm bank, package, and height 1 rank, height=30mm 60 6 data width of this assembly x64 40 7 reserved undefined 00 8 voltage interface level of this assembly sstl_1.8v 05 9 ddr2 sdram device cycle time at maximum support cas latency cl=5 3ns 30 10 ddr2 sdram device access time (t ac ) from clock at cl=5 0.45ns 45 11 dimm configuration type non ? ecc 00 12 refresh rate/type 7.8 s/self 82 13 primary ddrii sdram width x8 08 14 error checking ddrii sdram device width n/a 00 15 reserved undefined 00 16 ddr2 sdram device attributes: burst length supported 4,8 0c 17 ddr2 sdram device attributes: number of device banks 4 04 18 ddr2 sdram device attributes: cas latencies supported 3/4/5 38 19 dimm mechanical characteristics 4.10mm 01 20 ddr2 sdram dimm type information regular udimm (133.35mm) 02 21 ddr2 sdram module attributes: normal dimm 00 22 ddr2 sdram device attributes: general support weak driver 03 23 minimum clock cycle at cl=4 3.75ns 3d 24 maximum data access time (t ac ) from clock at cl=4 0.5ns 50 25 minimum clock cycle time at cl=3 5ns 50 26 maximum data access time (t ac ) from clock at cl=3 0.6ns 60 27 minimum row precharge time (t rp ) 15ns 3c 28 minimum row active to row active delay (t rrd ) 7.5ns 1e 29 minimum ras to cas delay (t rcd ) 15ns 3c 30 minimum active to precharge time (t ras ) 45ns 2d 31 module bank density 512mb 80 32 address and command input setup time before clock (t is ) 0.2ns 20 33 address and command input hold time after clock (t ih ) 0.275ns 27 34 data input setup time before clock (t ds ) 0.10ns 10 35 data input hold time after clock (t dh ) 0.175ns 17 36 write recovery time (t wr ) 15ns 3c 37 internal write to read command delay (t wtr ) 7.5ns 1e 38 internal read to precharge command delay (t rtp ) 7.5ns 1e 39 memory analysis probe characteristics undefined 00
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 8 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect ? part 2 of 2 (512mb) 64mx64 1 bank unbuffered ddr2 sdram dimm based on 64mx8, 4banks, 8k refresh, 1.8v ddr2 sdrams with spd spd entry value serial pd data entry (hexadecimal) byte description ddr2 -667 (-3c) ddr2 -667 (-3c) note 40 extension of byte 41 t rc and byte 42 t rfc the number below a decimal point of t rc and t rfc are 0, t rfc is less than 256ns 00 41 minimum core cycle time (t rc ) 60ns 3c 42 min. auto refresh command cycle time (t rfc ) 105ns 69 43 maximum clock cycle time (t ck max) 8ns 80 44 max. dqs-dq skew factor (t qhs ) 0.24ns 18 45 read data hold skew factor (t qhs ) 0.34ns 22 46-61 reserved undefined 00 62 spd revision 1.0 10 63 checksum data checksum data 6f 64-71 manufacturer?s jedec id code nanya 7f7f7f0b00000000 72 module manufacturing locat ion manufacturing code -- 73-91 module part number module part number in ascii -- 1 92-255 reserved undefined -- note: 1. m1y51264tu88a2b-3c ? 4d31593531323634545538384132422d3337420
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 9 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 1 of 2 (1gb) 128mx64 2 banks unbuffered ddr2 sdram dimm based on 64mx8, 4banks, 8k refresh, 1.8v ddr2 sdrams with spd spd entry value serial pd data entry (hexadecimal) note byte description ddr2 -667 (-3c) ddr2 -667 (-3c) 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type ddr2-sdram 08 3 number of row addresses on assembly 14 0e 4 number of column addresses on assembly 10 0a 5 number of dimm bank, package, and height 2 rank, height=30mm 61 6 data width of this assembly x64 40 7 reserved undefined 00 8 voltage interface level of this assembly sstl_1.8v 05 9 ddr2 sdram device cycle time at maximum support cas latency cl=5 3ns 30 10 ddr2 sdram device access time (t ac ) from clock at cl=5 0.45ns 45 11 dimm configuration type non - ecc 00 12 refresh rate/type 7.8 s/self 82 13 primary ddrii sdram width x8 08 14 error checking ddrii sdram device width n/a 00 15 reserved undefined 00 16 ddr2 sdram device attributes: burst length supported 4,8 0c 17 ddr2 sdram device attributes: number of device banks 4 04 18 ddr2 sdram device attributes: cas latencies supported 3/4/5 38 19 dimm mechanical characteristics 4.10mm 01 20 ddr2 sdram dimm type information regular udimm (133.35mm) 02 21 ddr2 sdram module attributes: normal dimm 00 22 ddr2 sdram device attributes: general support weak driver 03 23 minimum clock cycle at cl=4 3.75ns 3d 24 maximum data access time (t ac ) from clock at cl=4 0.5ns 50 25 minimum clock cycle time at cl=3 5ns 50 26 maximum data access time (t ac ) from clock at cl=3 0.6ns 60 27 minimum row precharge time (t rp ) 15ns 3c 28 minimum row active to row active delay (t rrd ) 7.5ns 1e 29 minimum ras to cas delay (t rcd ) 15ns 3c 30 minimum active to precharge time (t ras ) 45ns 2d 31 module bank density 512mb 80 32 address and command input setup time before clock (t is ) 0.2ns 20 33 address and command input hold time after clock (t ih ) 0.275ns 27 34 data input setup time before clock (t ds ) 0.10ns 10 35 data input hold time after clock (t dh ) 0.175ns 17 36 write recovery time (t wr ) 15ns 3c 37 internal write to read command delay (t wtr ) 7.5ns 1e 38 internal read to precharge command delay (t rtp ) 7.5ns 1e
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 10 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 2 of 2 (1gb) 128mx64 2 banks unbuffered ddr2 sdram dimm based on 64mx8, 4banks, 8k refresh, 1.8v ddr2 sdrams with spd spd entry value serial pd data entry (hexadecimal) byte description ddr2 -667 (-3c) ddr2 -667 (-3c) note 39 memory analysis probe characteristics undefined 00 40 extension of byte 41 t rc and byte 42 t rfc the number below a decimal point of t rc and t rfc are 0, t rfc is less than 256ns 00 41 minimum core cycle time (t rc ) 60ns 3c 42 min. auto refresh command cycle time (t rfc ) 105ns 69 43 maximum clock cycle time (t ck max) 8ns 80 44 max. dqs-dq skew factor (t dqs ) 0.24ns 18 45 read data hold skew factor (t qhs ) 0.34ns 22 46-61 reserved undefined 00 62 spd revision 1.0 10 63 checksum data checksum data 70 64-71 manufacturer?s jedec id code nanya 7f7f7f0b00000000 72 module manufacturing locat ion manufacturing code -- 73-91 module part number module part number in ascii -- 1 92-255 reserved undefined -- note: 1. M1Y1G64TU8HA2B-3C ? 4d325931473634545538484132422d33432020
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 11 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to vss -0.5 to 2.3 v v dd voltage on vdd supply relative to vss -1.0 to +2.3 v v ddq voltage on vddq supply relative to vss -0.5 to +2.3 v h stg storage humidity (without condensation) 5 to 95 % t a operating temperature (ambient) 0 to +70 c t stg storage temperature (plastic) -55 to +100 c note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent dam age to the device. this is stress rating only, and functional operation of the device at t hese or any other conditions abov e those indicated in the operat ional sections of this specification is not im plied. exposure to absolute maximum rating co nditions for extended periods may affect r eliability. dc operating conditions symbol parameter rating units note t case operating temperature (ambient) 0 to 95 c 1,2,3 t stg storage temperature (plastic) -55 to 100 c i l short circuit output current -5 to 5 a t opr module operating temperature range (ambient) 0 to 55 c h opr operating humidity (relative) 10 to 90 % note: 1. case temperature is measured at top and center side of any drams. 2. t case > 85 c ? t refi = 3.9 s 3. all dram specification only support 0 c < t case < 85 c dc electrical characteristics and operating conditions (t case = 0 c ~ 85 c; v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v, see ac characteristics) symbol parameter min max units notes v dd supply voltage 1.7 1.9 v 1 v ddq i/o supply voltage 1.7 1.9 v 1 v ss, v ssq supply voltage, i/o supply voltage 0 0 v v ref i/o reference voltage 0.49v ddq 0.51v ddq v 1, 2 v ih (dc) input high (logic1) voltage v ref + 0.125 v ddq + 0.3 v 1 v il (dc) input low (logic0) voltage -0.3 v ref - 0.125 v 1 note: 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. on die termination (odt) current symbol parameter min max units emrs(1) state 5 7.5 ma/dq a6=0, a2=1 iodto enabled odt current per dq odt is high; data bus inputs are floating 2.5 3.75 ma/dq a6=1, a2=0 10 15 ma/dq a6=0, a2=1 iodtt active odt current per dq odt is high; worst case of data bus inputs are stable or switching 5 7.5 ma/dq a6=1, a2=0
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 12 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1.8v 0.1v (512mb, 1 rank, 64mx8 ddr2 sdrams) symbol parameter/condition pc2-5300 (-3c) unit notes i dd0 operating current: one bank; active/precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 600 ma 1 i dd1 operating current: one bank; active/read/precharge; burst = 2; t rc = t rc (min); cl=2.5; t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle 720 ma 1 i dd2p precharge power-down standby current: all banks idle; power-down mode; cke v il (max); t ck = t ck (min) 40 ma 1 i dd2n idle standby current: cs v ih (min); all banks idle; cke v ih (min) ; t ck = t ck (min); address and control inputs changing once per clock cycle 400 ma 1 i dd2q precharge quiet standby current; all banks idle; t ck =t ck (idd); cke is high; cs is high; other control and address bus inputs are stable; data bus inputs are floating. 320 ma 1 i dd3pf active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck (min); fast pdn exit mrs(12) = 0ma 152 ma 1 i dd3ps active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck (min); slow pdn exit mrs(12) = 1ma 48 ma 1 i dd3n active standby current: one bank; active/precharge; cs v ih (min); cke v ih (min); t rc = t ras (max) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 400 ma 1 i dd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck (min); i out = 0ma 1040 ma 1 i dd4w operating current: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck (min) 1120 ma 1 i dd5 auto-refresh current: t rc = t rfc (min) 1280 ma 1 i dd6 self-refresh current: cke 0.2v 40 ma 1 i dd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min); i out = 0ma. 1360 ma 1 note: 1. module idd was calculated from component idd. it may different from the actual measurement.
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 13 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1.8v 0.1v (1gb, 2 ranks, 64mx8 ddr2 sdrams) symbol parameter/condition pc2-5300 (-3c) unit notes i dd0 operating current: one bank; active/precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1000 ma 1 i dd1 operating current: one bank; active/read/precharge; burst = 2; t rc = t rc (min); cl=2.5; t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle 1120 ma 1 i dd2p precharge power-down standby current: all banks idle; power-down mode; cke v il (max); t ck = t ck (min) 80 ma 1 i dd2n idle standby current: cs v ih (min); all banks idle; cke v ih (min) ; t ck = t ck (min); address and control inputs changing once per clock cycle 800 ma 1 i dd2q precharge quiet standby current; all banks idle; t ck =t ck (idd); cke is high; cs is high; other control and address bus inputs are stable; data bus inputs are floating. 640 ma 1 i dd3pf active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck (min); fast pdn exit mrs(12) = 0ma 304 ma 1 i dd3ps active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck (min); slow pdn exit mrs(12) = 1ma 96 ma 1 i dd3n active standby current: one bank; active/precharge; cs v ih (min); cke v ih (min); t rc = t ras (max) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 800 ma 1 i dd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck (min); i out = 0ma 1440 ma 1 i dd4w operating current: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck (min) 1520 ma 1 i dd5 auto-refresh current: t rc = t rfc (min) 1680 ma 1 i dd6 self-refresh current: cke 0.2v 80 ma 1 i dd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min); i out = 0ma. 1760 ma 1 note: 1. module idd was calculated from component idd. it may different from the actual measurement.
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 14 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing specifications for ddr2 sdram devices used on module (t case = 0 c ~ 85 c; v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v, see ac characteristics) (part 1 of 2) -3c symbol parameter min. max. unit t ac dq output access time from ck/ ck -0.45 +0.45 ns t dqsck dqs output access time from ck/ ck -0.4 +0.4 ns t ch ck high-level width 0.45 0.55 t ck t cl ck low-level width 0.45 0.55 t ck t hp minimum half clk period for any given cycle; defined by clk high (t ch) or clk low (t cl ) time t ch or t cl - t ck t ck cl=3 3 8 ns t ck clock cycle time cl=4, 5 3 8 ns t dh dq and dm input hold time(differential data strobe) 0.175 - ns t ds dq and dm input setup time(differential data strobe) 0.1 - ns t ipw input pulse width 0.6 - t ck t dipw dq and dm input pulse width (each input) 0.35 - t ck t hz data-out high-impedance time from ck/ ck - t acmax ns t lz(dq) data-out low-impedance time from ck/ ck 2t acmin t acmax ns t lz(dqs) dqs low-impedance time from ck/ ck t acmin t acmax ns t dqsq dqs-dq skew (dqs & associated dq signals) 0.24 - ns t qhs data hold skew factor 0.34 - ns t qh data output hold time from dqs t hp - t qhs - ns t dqss write command to 1st dqs latching transition -0.25 +0.25 t ck t dqsl,(h) dqs input low (high) pulse width (write cycle) 0.35 - t ck t dss dqs falling edge to ck setup time (write cycle) 0.2 - t ck t dsh dqs falling edge hold time from ck (write cycle) 0.2 - t ck t mrd mode register set command cycle time 2 - t ck t wpst write postamble 0.40 0.60 t ck t wpre write preamble 0.35 - t ck t ih address and control input hold time 0.275 - ns t is address and control input setup time 0.20 - ns t rpre read preamble 0.90 1.10 t ck t rpst read postamble 0.40 0.60 t ck t rrd active bank a to active bank b command 7.5 ns t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck + t ih - ns average periodic refresh interval (85oc < t case 95oc) - 3.9 s t refi average periodic refresh interval (0oc t case 85oc) - 7.8 s t oit ocd drive mode output delay 0 12 ns t rfc auto-refresh to active/auto-refresh command period 105 - ns t ccd cas to cas 2 t ck
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 15 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing specifications for ddr2 sdram devices used on module (t case = 0 c ~ 85 c; v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v, see ac characteristics) (part 2 of 2) -3c symbol parameter min. max. unit t wr write recovery time without auto-precharge 15 - ns wr write recovery time with auto-precharge t wr /t ck t ck t dal auto precharge write recovery + precharge time wr+t rp - t ck t wtr internal write to read command delay 7.5 - ns t rtp internal read to precharge command delay 7.5 - ns t xsnr exit self refresh to a non-read command t rfc +10 - ns t xsrd exit self refresh to a read command 200 - t ck t xp exit precharge power down to any non- read command 2 - t ck t xard exit active power down to read command 2 - t ck t xards exit active power down to read command 7-al - t ck t cke cke minimum pulse width 3 - t ck odt t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac (min) t ac (max) +0.7 ns t aonpd odt turn-on (power down mode) t ac (min) +2 2t ck + t ac(max) +1 ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac(min) t ac(max) +0.6 ns t aofpd odt turn-off (power down mode) t ac (min) +2 2.5t ck + t ac(max) +1 ns t anpd odt to power down entry latency 3 - t ck t axpd odt power down exit latency 8 - t ck speed grade definition t ras row active time 45 70,000 ns t rc row cycle time 60 - ns t rcd ras to cas delay 15 - ns t rp row precharge time 15 - ns
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 16 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimensions (512mb, 1 rank, 64mx8 ddr sdrams) front 1.50 detail a 0.039 detail b 0.8 width back 0.059 3.80 0.15 0.157 4.00 0.031 1.00 pitch detail a detail b 0.098 2.5 10.0 0.394 133.35 131.35 128.95 5.250 5.171 5.077 17.80 3.0 0.118 0.700 30.00 1.180 (2x) 4.00 0.157 note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches) side 3.81 (front) 1.27 0.125 max. 0.050
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 17 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimensions (1gb, 2 rank, 64mx8 ddr sdrams) front 1.50 detail a 0.039 detail b 0.8 width back 0.059 3.80 0.15 0.157 4.00 0.031 1.00 pitch detail a detail b 0.098 2.5 10.0 0.394 133.35 131.35 128.95 5.250 5.171 5.077 17.80 3.0 0.118 0.700 30.00 1.180 (2x) 4.00 0.157 note: all dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. units: millimeters (inches) side 4.00 (front) 1.27 0.157 max. 0.050
m1y1g64tu8ha2b / m1y51264tu88a2b 1gb: 128m x 64 / 512mb: 64m x 64 unbuffered ddr2 sdram dimm rev 1.0 18 08/2005 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. revision log rev date modification 0.1 05/2005 preliminary release. 0.2 07/2005 update spd, idd data, timing parameter, and operating condition. 1.0 08/2005 official release for elixir nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 please visit our home page for more information: www.elixir-memory.com

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